![]() The Synplify Premier tool automates industry methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries. ![]() Industry standards including DO-254, IEC 61508 and ISO 26262 define functional safety and error mitigation strategies for the creation and validation of high reliability systems. As FPGA device geometries shrink, this solution is becoming a “must have” for systems deployed in industrial, medical, automotive, communications, military and aerospace applications. These designs become resistant to radiation-induced errors and other single bit flips that might otherwise result in incorrect operation or, even, system lock-up. Synopsys Synplify® Premier software offers FPGA designers an automated means to build into their design functional safety, high uptimes, and highly reliable design operation. ![]()
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